Microprocessors often use instruction pipelining to increase instruction throughput. An instruction pipeline processes several instructions through different stages of instruction execution concurrently, using an assembly line-type approach. Furthermore, these instructions may be executed in a dynamically scheduled (e.g., out-of-order) processor.
In the Itanium Architecture, an instruction may include a “qualifying predicate”. The value of the qualifying predicate determines whether the instruction is executed or not. Itanium Architecture uses 64 predicate registers.
The performance of out-of-order computers using predicate registers, may be degraded by dependencies. A dependency exists between two instructions if the execution of one depends upon the results of executing the other. Thus, each instruction has the potential to stall later instructions that depend on it. Therefore, in some applications, predicates may be predicted in advance to remove the dependencies. However, verifying predicate prediction and maintaining the architecturally correct predicate registers are often cumbersome and tedious process because each predicate register must be verified and maintained individually.